Why do we need virtual interfaces in system verilog?

SystemVerilog
15

In reply to mallick1:

I disagree with your statement "you can easily drive a module wire from within a task member of a class as follows

task drive();
   @(posedge clk)
      dut.signal <= 1;

Below is an example from my SVA book on verifying assertions. See the task is_illegal;

 
module ld_reg #(SIZE=8) 
    (input logic clk, ld, 
     input logic[SIZE-1:0] d_in, 
     output logic[SIZE-1:0] r_out, d_out,k_out, 
     inout logic[SIZE-1:0] data1, data2, data3); 

    logic a, b=1'b1, oe; // local variable 
    wire[SIZE-1:0] wdata1, wdata2, wdata3;
    always @ (posedge clk) begin : FF_LD
        // The begin statement is only needed
        // if multiple statements in body of always 
        r_out <= d_in;
        // data1 <= d_in; // illegal 
        // line above:  A net is not a legal lvalue in this context
        // wdata1 = d_in; // illegal 
        // line above:  A net is not a legal lvalue in this context
        //assign wdata3 = 'bZ; // illegal 
        assign d_out=oe ? 8'b101_1110 : 'bZ;      
    end : FF_LD
    
    task is_illegal; 
      @ (posedge clk)  
        data1 <= d_in; // Illegal reference to net "data1".
        wdata1 <= d_in; // Illegal reference to net "wdata1".
     endtask  
     
    assign data1 = oe ? 8'b101_0000 : 'bZ; 
    assign k_out=8'b10X_XZZ0;  
endmodule : ld_reg

I explain in the book the following:
Assignments to inout port or module wire:

  1. Module ports defined as direction inout and internal nets (e.g., wire) can be driven by the continuous “assign” statement inside a module or interface. For example:
    assign data1 = oe ? 8’b101_0000 : 'bZ; // 
    However, the assign onto nets within an always block or task is illegal:
    2)Module ports defined as direction output, inout, and internal nets (e.g., wire) can be driven by a clocking block.
    Ben Cohen
    http://www.systemverilog.us/ ben@systemverilog.us
  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115