Why do we need virtual interfaces in system verilog?

In reply to mallick1:

Well, you dont. You can easily connect module ports to class members by dotting into the module.

This is the crux of the issue. If you are putting classes in a package, you can’t have hierarchical references (dotted names) inside a package, and even if not using packages, you should not be putting in hierarchical reference inside to make your testbench re-usable. A `define won’t work if several instances of the class needs to connect to different places in the design.