Why do we need virtual interfaces in system verilog?

In reply to mallick1:

Well, you dont. You can easily connect module ports to class members by dotting into the module.
You could also 'define the module signal in order to get a single place to change when you change your class based TB to another module.

virtual Interface_Name foo; can save the name for you, which you can use as a generic foo.

Can you elaborate on those above?