In reply to mseyunni:
The question is why you need “virtual interface” in System Verilog.
Well, you dont. You can easily connect module ports to class members by dotting into the module.
You could also 'define the module signal in order to get a single place to change when you change your class based TB to another module.
But people use it because it is a variable that refers to the interface’s dotted net.
virtual Interface_Name foo; can save the name for you, which you can use as a generic foo.
Cheers.
Soummya