Why bind method is required in SVA?

SystemVerilog
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1

Hi All,
Why bind method is really necessary in SVA ? As we can achieve the same through the hierarchical path.
bind fifo2: u1
pLib_fifo1 p1 (.wptr(qptr), .rptr(iptr), .cnt(word_counter));

the same thing cab be achieved , if we want to access the path for the fifo module.

define path tb_top.fifo_inst
pLib_fifo1 p1 (.wptr(path.qptr), .rptr(path.iptr), .cnt(`path.word_counter));

Thanks,
Abhijeet

2

You are correct in that the same functionality could be achieved, but there are still a number of advantages when using the bind construct:

  • The scope of the assertions and other messages are correlated to the bound target instance. Makes it much easier to understand reports and aids debugging.
  • You can bind to target all instances of a particular target module instead of explicitly having to list each one individually.
  • Easier to read statement when the port list is big.