Why are UVM components called components?

UVM
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1

Hi All,

I was curious to know why UVM components are called components?

Also, why can’t we have a delay before run_test() in a UVM environment?

Your response will be highly appreciated.

Thanks!

2

In reply to LearningDV:

The term “component” in UVM comes from similar usage in SystemC and VHDL, which in turn comes from its usage in PCB design. A component is a piece of a larger design that together makes up the structural model of your design, In the UVM case, the design is the testbench. Your drivers, monitors, and agents are components that make up the structure of your testbench.

Requiring that you call run_test() at time 0 ensures that the run_phase starts at time 0. This enforces a methodology that makes it easier to integrate IP from many sources because everyone shares the same concept of the test beginning at time 0.

3

Hi Dave,

Thank you for your response.

Do you know of any good source that talks more about run_test() required to be called without any delay?

Thanks!