White space between macro definition and inline comment?

SystemVerilog
,
1

If a macro is defined with a comment like this:

`define foo bar   // comment here

Should `foo be just:

->bar<-

Or should it be:

->bar     <-

It seems I am seeing inconsistent interpretation from one simulator to the next.

2

In reply to jkc120:

I don’t think this issue has ever been resolved.
See http://www.eda-stds.org/mantis/view.php?id=1339 .

3

In reply to shalom:

Yeah, I can see how it would be a legacy concern from the one perspective but rather nebulous and potentially limiting if a macro NEEDS the white space.

So it’s just one of those cases where, to have portable code, you need to use the least common denominator code that would work with both? :)

Thanks for the pointer!