Since there is a write() function in the uvm_analaysis_port itself, and also we user will define a corresponding write() function in the component that is connected with that uvm_analaysis_port, so I feel confused, which “write” function is invoked when executing ap.write() in a component like Monitor? Is there any relation between the two write() functions? I can not comprehend this when referring to source code and the DOC called class reference of UVM.
In reply to Marina:
The analysis_port can have multiple subscribers. When the monitor calls the analysis_port’s write() function, the analysis_port will then call the write() function of each subscriber.
In reply to cgales:
Yes, I know an analysis_port can have multiple subscribers.
#When the monitor calls the analysis_port’s write() function, the analysis_port will then call the write() function of each subscriber.# Here you mean analysis_port’s internal write() function will invoke write_subscriberA() function of subscriber A and write_subscriberB() function of subscriber B? How is this implemented in the write() of analysis_port?
Thank you!
In reply to Marina:
Look at the source code for the analysis_port (src/tlm1/uvm_analysis_port.svh).
In reply to cgales:
I can’t comprehend that source code, the write() function of tif is just void, it implements nothing in it.
In reply to Marina:
The implementation of TLM (analysis ports, etc) in UVM is complicated and involves lots of redirection. When UVM was created, SystemVerilog did not have multiple inheritance and requires an intermediate umm_*imps class object that redirects the analysis_port.write to the write() defined in the subscriber class.
Unfortunately, it’s too late to change the UVM and take advantage of newer features that would make this much simpler.
In reply to dave_59:
Thank you.