Which registers sequences/tests should we run for verifying completely registers functionality?

UVM
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14

In reply to dddvlsique:

For RO registers again you could follows these steps but then it will be gain protocol based:

  1. Backdoor read the RO reg using backdoor or user defined backdoor as suggested by chr_sue
  2. Issue a write using protocol based sequences (if an error is expected because enabled in the RTL logic then check the error)
  3. Backdoor read the RO reg using backdoor or user defined backdoor as suggested by chr_sue

RO registers have their default values specified in the register descriptors so you can easily check it out. Regards