The SystemVerilog DPI requires that C code calling SV code must have originated from SV code that called the C code. This is because the SystemVerilog simulation must establish a context for the C code that includes timing and scope information that does not exist in C code. Calling C code from SV code establishes that context in the C code.
There are still a number of ways to control a test from C code. See the following links for more information:
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI