I’m relatively new to verification using systemVerilog having come from a directed-testing based verilog background.
If I have a modular class-based systemVerilog testbench designed for random testing, that does not use UVM but uses UVM-like architectures with an environment, agent, generator, driver, monitor, scoreboard etc that utilizes transaction classes which are normally randomized in the generator, how do I adapt this testbench to then run directed tests where a very specific sequence of inputs (rather than random) is required?
Is there a general recommendation as to how to do this? Do I write a completely new testbench that throws out all the generator, driver stuff or can a directed test logically reside inside one of the standard classes - e.g. should I create a new task inside the driver to drive the necessary sequence? This might be done by creating a derived version of the driver where it’s main task is replaced by a directed test. Would this be a logical approach or is there a standard well recognised way of adapting a testbench designed for random testing to make it capable of driving very specific and sometimes long sequences of directed inputs?
Any thoughts on this welcome!