In reply to dave_59:
Hi Dave,
Thanks for the answer.
My suggestion is that you stick with 2 state data types in your testbench unless you have a specific need to generate or propagate X or Z states.
What about detecting the ‘x’ driven from the design. We will have logic defined in the interface to catch these. But, if we define 2-state types are we not missing on checking those x’s in the testbench.
Performance of 2-state versus 4-state simulation is debatable
Could you explain why the performance improvement is debatable. I read somewhere that 2-states do have performance benefit over the 4-state.
SystemVerilog is very relaxed (some will say too relaxed) when it comes to operations requiring 2 or 4 state types. Only when passing arguments by reference are you required to match a 2 or 4 state type
I am not sure I understood this. Could you explain why do you need to match the types when passing by ref. What problems do you have if not matched ?
Regards,
Madhu