My suggestion is that you stick with 2 state data types in your testbench unless you have a specific need to generate or propagate X or Z states. This eliminates any chance of introducing these extra states when your code has not been designed to deal with it. Performance of 2-state versus 4-state simulation is debatable, but is certainly takes more memory to represent 4-state values.
Whether a loop variable is signed or unsigned should not really matter, unless of course, you need to loop through values that only one of those choices can represent. A place you do need to be cautious about using signed types is in constraints and assertions. It is very easy for unintended negative values to pass through (e.g. you wrote “a < 3” expecting only the values 0,1, and 2 to succeed).
SystemVerilog is very relaxed (some will say too relaxed) when it comes to operations requiring 2 or 4 state types. Only when passing arguments by reference are you required to match a 2 or 4 state type.
Another place you should use int is when using the DPI-C. It is much more efficient for the DPI to pass C-compatible data types like int across the language boundary.