I’ve learned how to build a UVM platform. But right now I am just building a lot of types of interfaces and sequences and drivers and then drive DUT. I can’t find the difference between UVM and normal SV testbench. I don’t really feel the need to use factory or RAL. For factory and configuration, I can just write a bunch of SV tasks and use `ifdef to choose the task I want to run instead. For RAL, I don’t understand why should we access DUT registers to build a model solely based on spec. I find myself spending way more time if I have to create so much sequences and drivers and use virtual sequencer to schedule them. For me normal SV task is just as good as if not better than uvm sequence. I watched lots of tutorials but they mostly just teach you how to do it but not how to do it effieciently. I think I don’t really find the essence and importance of UVM and want to seek help. Thanks!
In reply to patrick1258:
I think when it comes to common usage and understanding for all in an easier way,
like in SV you can write your UVC/TB in your logic/flow, when it is given to others/integrator it may take time to understand and implement in their environment, hence when you use UVM it will be easier since it is predefined flow,
It provides may methods and mechanisms to ease the coding and usage, whereas SV is abstract,
Factory is useful when you want to override and has some methods which can be used to control the log displays,
TLM communication is little different than the IPC’s we use in SV tb.
In reply to patrick1258:
I’ve learned how to build a UVM platform. But right now I am just building a lot of types of interfaces and sequences and drivers and then drive DUT. I can’t find the difference between UVM and normal SV testbench. I don’t really feel the need to use factory or RAL. For factory and configuration, I can just write a bunch of SV tasks and use `ifdef to choose the task I want to run instead. For RAL, I don’t understand why should we access DUT registers to build a model solely based on spec. I find myself spending way more time if I have to create so much sequences and drivers and use virtual sequencer to schedule them. For me normal SV task is just as good as if not better than uvm sequence. I watched lots of tutorials but they mostly just teach you how to do it but not how to do it effieciently. I think I don’t really find the essence and importance of UVM and want to seek help. Thanks!
If you are writing your testbenches as you describe you do not profit from the benfits of the UVM.
In my eyes there a 3 main benefits:
(1) Best practice: Consistency, uniformity, don’t reinvent the wheel, avoid pitfalls
(2) reuse: Verification IP, verification environments, tests, people, knowhow
(3) simulation performance: by employing strongly TLM you are reucing the the number of evnts during your simulation resulting in a tremendous better simulation performance.