I want to generate jitter and glitches in my clock ,so I used UVM env to generate clock and pass it to the design.
It is working fine but I might integrate the same clock in other Tbs.
I came across SV scheduling where they have advised against using uvm env for clock generation.I can understand why program blocks are not to be used as it schedules in reactive region but there are no details regarding region in which the uvm env should be evaluated by simulator.
Can some one tell me scenario where clock generated using uvm will create problem.
In reply to Sreeveni Pulinkuzhi:
The scheduling region of the UVM is dictated by the region of the initial block where run_test() gets called from. I recommend never using program blocks.
The main concern with clock generators is they generate some of the most activity in a simulation, so you need to code carefully to get the best performance. You might want to review it and use your tools profiling capabilities if performance becomes an issue for your simulations.
In reply to dave_59:
As run test is called in intial block of top module,Im assuming all simulators would run class code in active region depending on blocking and nonblocking region assigment flow along with rtl code.
So even if I generate clock in sv module or uvm class they would be computed similarly.Is my understanding correct.
My concern was if clock generated in module would execute code differently than clock generated in uvm class based environment.