I have seen while running a simulation we used give seed value by using -seed or -svseed switches. What changes will it make during our simulation and why is it required?
In reply to Raj Guru:
Constrained Random Verification is essentially taking a random sample of all the possible stimulus to your design. The seed determines the sequence of random numbers that get generated.
Normally you want to run your tests with a different seed each time to increase the stimulus sample size. However, if one of your tests fails, you want to run with the same seed to make sure the sequence of stimulus remains exactly the same for debugging. And you want to run the the same sequence after making the fix. These switch control whether you use a different or the same seed.
You might want to see the introduction to this course:
https://verificationacademy.com/sessions/verilog-basics-for-systemverilog-constrained-random-verification