In reply to gupta409:
It looks you have correct codes to write mem into test file and append one data per loop to text file. I reproduced your codes simply as below and it works. The only differences are that 1) I use randomize(instrn_wr) to replace your transaction item “req.instrn” and 2) I add read text file paragraph to show the data appended correctly.
Can you please clarify what do you mean
When I run this code only the last sequence in the text file gets written and consumed by the DUT.
Have you seen req.instrn value change with the uvm_info message?
import uvm_pkg::*;
`include "uvm_macros.svh"
module tb();
initial run_phase();
task run_phase();
bit drv_clk;
reg[15:0]mem[0:18];
int fin;
int i;
//bit [15:0] eop =16'hFFFF;
bit [15:0] instrn_wr, instrn_rd;
int loop;
integer code;
//Set initial instructions.txt file
mem[0]=16'h9A35;
mem[1]=16'h9A7F;
mem[2]=16'h9A85;
mem[3]=16'h9AC0;
mem[4]=16'h9B0B;
mem[5]=16'h9B73;
mem[6]=16'h9BBC;
mem[7]=16'h9BC1;
mem[8]=16'h9C04;
mem[9]=16'h9C40;
mem[10]=16'h9C81;
mem[11]=16'h9CEB;
mem[12]=16'h9D11;
mem[13]=16'h9D40;
mem[14]=16'h9D82;
mem[15]=16'h9DD4;
mem[16]=16'hEFFF;
mem[17]=16'hEFFF;
mem[18]=16'hEFFF;
$writememh("instructions.txt",mem);
// Now drive normal traffic
while (loop<=3) begin
fin=$fopen("instructions.txt","a");
void'(randomize(instrn_wr));
$fdisplayh(fin, instrn_wr);
$fclose(fin);
`uvm_info ("PASS ", $sformatf("loop=%0d instrn_wr=%h",loop, instrn_wr), UVM_LOW)
//-----------------read the text file to show data appended--------
fin=$fopen("instructions.txt","r");
while(!$feof(fin)) begin
code = $fscanf(fin, "%0h", instrn_rd);
//if (loop==3) //open these two lines will show the whole text file contents @loop 3
// `uvm_info ("PASS ", $sformatf("loop=%0d instrn_rd=%h",loop, instrn_rd), UVM_LOW)
end
$fclose(fin);
`uvm_info ("PASS ", $sformatf("loop=%0d instrn_rd=%h",loop, instrn_rd), UVM_LOW)
//------------------------------------------------------------------
for(i=0;i<25;i++)begin
#5;
drv_clk = ~drv_clk;
end
loop++;
end
endtask
endmodule
Simulation log:
UVM_INFO testbench.sv(45) @ 0: reporter [PASS ] loop=0 instrn_wr=2964
UVM_INFO testbench.sv(55) @ 0: reporter [PASS ] loop=0 instrn_rd=2964
UVM_INFO testbench.sv(45) @ 125: reporter [PASS ] loop=1 instrn_wr=080b
UVM_INFO testbench.sv(55) @ 125: reporter [PASS ] loop=1 instrn_rd=080b
UVM_INFO testbench.sv(45) @ 250: reporter [PASS ] loop=2 instrn_wr=4e3c
UVM_INFO testbench.sv(55) @ 250: reporter [PASS ] loop=2 instrn_rd=4e3c
UVM_INFO testbench.sv(45) @ 375: reporter [PASS ] loop=3 instrn_wr=2eff
UVM_INFO testbench.sv(55) @ 375: reporter [PASS ] loop=3 instrn_rd=2eff