In reply to chr_sue:
Register value checking should be done passively to ensure vertical reuse. Checking in a sequence or test that you read what you expect is an active/directed style checking that will not work without active control. The way I’ve often seen it, at least for block level environments, is that the test should read all the registers at the end of the test or even during the run-time of the test. This will cause expected/observed checking. Configuration registers are rather straightforward since the adapter sniffs the writes and updates it’s mirrored/expected value. Status registers, however, are more challenging. To passively predict status registers can require a more complicated prediction model to set the expected value when the prediction model determines that the status bit should be set. Also, status registers can be racey and sometimes it’s hard to set the expected value at the right time and avoid false negative mismatches. Sometimes people use white boxing to overcome racey mismatches of the expected values of volatile status registers, but white-boxing is never ideal.