In reply to dave_59:
Hi Dave,
From SV LRM, 24.4 Eliminating testbench races,
It is important to understand that simply sampling input signals (or setting nonzero skews on
clocking block inputs) does not eliminate the potential for races. Proper input sampling only addresses a single clocking block. With multiple clocks, the arbitrary order in which overlapping or simultaneous clocks are processed is still a potential source for races. The program construct addresses this issue by scheduling its execution in the Reactive region, after all design events have been processed, including clocks driven by nonblocking assignments.
Does it mean that Program block is mandatory while dealing with multiple clocks/clocking blocks ?