What is the proper way to drive a combinational ACK signal?

SystemVerilog
1

Suppose I have a simple protocol of req and ack.
DUT assert req and deassert it when ack is valid.
My driver should drive the ack.

simple driver will look like that:

forever
begin
    @(vif.drv_cb iff vif.drv_cb.req);
    vif.drv_cb.ack <= 1;
    @(vif.drv_cb);
    vif.drv_cb.ack <= 0;
end

In this case, ACK will be asserted one clock cycle after REQ.
However, there are cases when I want to model a combinational ACK (i.e., ACK goes high in the same cycle REQ is asserted).

The following code does the trick, but I’m not feeling comfortable with it

forever
begin
    wait(vif.req);        
    vif.ack <= 1;
    @(vif.drv_cb);
    vif.ack <= 0;
end

I would like to receive any comments or better solutions.