What is the primary difference between Virtual class and Interface class?

SystemVerilog
1

is there any major difference between Virtual class Vs Interface class?

I can think of two differences:

  1. With the Interface class we can have multiple inheritances (implements) of the base class.
  2. The interface class only contains pure virtual functions.

But what is the practical use case of each of these classes?

Thanks :)

2

In reply to abhpan:

https://verificationacademy.com/forums/systemverilog/interface-class-and-abstract-class-and-when-use-which-one#reply-76813

3

In reply to dave_59:

Thank you Dave for your response.
I’ll go through the link.