What is the number of test vectors required to test a priority encoder with “n” inputs?

SystemVerilog
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1

Let us say we have a 8 to 3 priority encoder. What is the minimum number of test vectors I need to fully verify it it?

Here is what I was thinking:

  • All inputs at 1 (1 vector)
  • All inputs at zero (1 vector)
  • Each input set 1 and the rest are at 0 (8 vectors)
  • Each input set to 0 and rest are set to 1

How do I randomly cover other combinations, like 2 or 3 or 4 inputs set to 1 and vice versa?

Any ideas?

2

In reply to Verif Engg:

What is the minimum number of test vectors I need to fully verify it it?

Of course, the answer is 2^n. Formal verification will be a good application for this.

How do I randomly cover other combinations, like 2 or 3 or 4 inputs set to 1 and vice versa?

You could use something like the following code:


import uvm_pkg::*; `include "uvm_macros.svh" 
class C; 
  rand bit[7:0] s, w;
  constraint cs2 {$countones(s)==2; // number on ONEs ==2
	};
  constraint cw3_zeros {$countones(~w)==3; // Number of ZEROs==3
		};
endclass
module top; 
	bit clk, a, b;  
	C c;  
	initial forever #10 clk=!clk;  
 
	initial begin 
		c=new();
		repeat(200) begin 
			@(posedge clk); 
			if (!randomize(c))  `uvm_error("MYERR", "This is a randomize error")			
			$display("c.s=%b c.w=%b", c.s, c.w);
		end 
		$stop; 
	end 
endmodule  
 // simulation results 
c.s=00000101 c.w=01101110
# c.s=00100100 c.w=11010110
# c.s=00000011 c.w=00110111
# c.s=00010100 c.w=01101110
# c.s=00110000 c.w=00101111
# c.s=00101000 c.w=11101001
# c.s=10001000 c.w=01111001
# c.s=00001100 c.w=10011011
# c.s=10000001 c.w=01101101
# c.s=01010000 c.w=01111010
# c.s=10001000 c.w=11010011
# c.s=10000100 c.w=00110111
# c.s=10000010 c.w=11100011
# c.s=10100000 c.w=00101111
# c.s=01100000 c.w=00101111

Ben Cohen
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