I have worked on various designs and no one in my team did gate level simulations. Is there really need of doing gate level simulations?
If all functional issues are resolved in functional verification using SV-UVM, Designs are synthesizing finely and all timings are met during synthesis , what is really left to do in Gate level simulations? why should one do gate level simulations ?
In reply to tro:
I need to run gate-level sims (without timing) about once a year. In all cases that I’m doing this, it’s to debug a likely synthesis/simulation mismatch by some vendor’s tool. In short, I’m validating a vendor’s tools. This should be unnecessary, but well, that’s engineering.
Gate level simulations, with (SDF) timing? I’ve not run any in over 20 years.
There’s a vocal set of folks that really sell gate-level simulations, and the benefits that they offer. I remain unconvinced that the benefits outweigh the costs. The simulations are just too slow these days, and there’s other ways of solving the problems that gate-level sims are offering. In fact, I heard a rumor recently that one FPGA vendor is no longer even offering gate-level simulations as possible in its supported flows.
When I did ASICs (more than a decade ago, so my knowledge is a bit out-of-date), gate-level simulations were popular with tools that tweaked the netlists post synthesis. One example - test-insertion tools (ATPG/BIST/etc). Other examples could include physical implementation time DRC tweaks. But I’m thinking formal tools could fill this niche easier/safer/more complete/quicker these days.
Regards,
Mark