what is the necessity of generate block in verilog?
what are its uses
what is the necessity of generate block in verilog?
what are its uses
In reply to lalithjithan:
Generate is mainly used for conditional inclusion or exclusion of any logic, module instantiation etc., usually based on the parameter values. It can also be used to code repetitive logic/multiple module instantiations in a concise manner. Note that the evaluation of Generate happens at elaboration time.
Refer “27. Generate constructs” of SV 1800-2012 for more details.
Thankyou