In reply to Subhra Bera:
sequence iicBitSeq;
c ##1 b[*3]; endsequence
sequence iicByteSeq;
@(posedge clk)
##0 ( 1 [*1:$] ##0 iicBitSeq ) [*3] ;
endsequence
// Using 3 instead of $
// (1[*1:3] ##0 iicBitSeq) //is same as
(1[*1] ##0 iicBitSeq) or (1[*2] ##0 iicBitSeq) or (1[*3] ##0 iicBitSeq)
// same as
(##0 iicBitSeq) or (##1 iicBitSeq) or (##2 iicBitSeq)
// NOTE: 1'b1[*2] ##0 b // same as
// (1'b1 ##1 1'b1) ##0 b // same as
// ##1 b // 1'b1 ##0 b // same as b
##0 ( 1 [*1:$] ##0 iicBitSeq ) [*3] // same as
(##0 iicBitSeq) or (##1 iicBitSeq) or (##2 iicBitSeq)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115