What is the expected output and how?

SystemVerilog
,
1 
int k;

for(int i=0;i<11;i++,k++) begin
   $display("value of i %0d k %0d",i,k);
   i++;
  k=i;
 end

$display("value of k is %0d",k);
1 Like
2

I would expect to get a syntax error with the coach shown. It is not contained in a module, nor is there a procedural block started.

Please show a complete example and give us your intended output.

3

Hi @dave_59 ,

considering the code is in a procedural block where k is uninitialized, what would be the expected output is what i want !

4

Please tell us the output put you expect to see and why it difference from the actual output you get.