What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

SystemVerilog
10

In reply to puttasatish:

Hi puttasatish,
If I give the same code with no delay. I’m getting below results
the sum is 5
the sum is 7.
Do you know what could be the reason?

module test();
 
task add(int a, int b);
	//#2;
	$display("the sum is %0d", a+b);
endtask
 
initial
	fork
		begin
			add(2,3);
		end
		begin
			//#1;
			add(3,4);
		end
	join
endmodule