What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

In reply to Have_A_Doubt:
Declaring any function or task with an explicit static lifetime is something you should never need to do in either Verilog or SystemVerilog. If it were not for the mandate to be 100% backward compatibility with Verilog-2001, it could have been eliminated from SystemVerilog.

Because the
class
is a new construct in SystemVerilog, we had the opportunity to change the default lifetime and eliminate the confusion between ‘static function’ and ‘function static’. Anyone declaring a function with a static lifetime in a class would most likely be making a mistake thinking they were declaring a static method. By making it illegal, their mistake is caught much earlier.