In the test you are starting simply one or more sequences, in most cases a virtual sequence.
What is your objective sending data upwards in the UVM hierarchy?
The DUT will send the data and I have an interface to instance it…
it’s like a simple design and it only has one driver to drive the input of this design and one monitor to receive the output data. I just wonder if any easier way to get the data in the test .
If you want to use an UVM environment you need a sequencer/driver pair to stimulate your design. A sequence will be executed on the sequencer, generating seq_items which will be processed in the driver, creating the pin wiggles. The test contains your UVMenvironment and specifies which sequence will be executed.
I believe you have a different understanding of test.
I have a simple driver and a simple sqr to send item. my question is how to get the data from monitor in the test directly. do you mean we can just use below method to do it ?
in my_test.svh file :
my_env env_inst;
logic data = env_inst.agt_inst.mon_inst.data;