what is the difference between sv and uvm?
In reply to swethasundararaj:
We can not compare SV and UVM as UVM is a methodology in which a rich set of functions are developed in its library using SV features to make code re-usable and well structured.
In reply to bdreku:
To be a little bit more precisely: SV is the only Hardware Design and Verification Language (HDVL). It consists of 3 main parts
- SV-HDL Hardware Design Language, it is an enhancement of Verilog.
- SV-Assertions: These are language constructs for implementing assertions (you might know PSL)
- SV-HVL: Hardware Verification Language: these are all the class-based and other constructs useful for verification.
UVM = Universal Verification Methodology is not language, but a SV class library, developed for verification.
First and foremost is a problem that is glaringly obvious to anyone who’s tried learning SystemVerilog and the UVM (or one of the other VMs over the years): it’s difficult and time consuming to learn SystemVerilog and any of the VMs… especially if you have never used a verification language before. Folks with limited software backgrounds (read: most design and verification engineers) find seemingly simple concepts like inheritance and factories to be mind boggling, even if they won’t admit it. And folks with deep software backgrounds will find SystemVerilog an absolute pit of despair when compared with modern languages such as Python and Ruby, and the UVM complex in a way that clearly is meant to patch over serious deficiencies in the underlying language. Plus, any testbench that has to deal with multi-language issues is clearly out of luck in the simplicity and ease of use department.
Now that the UVM has arrived and the methodology bickering between the major vendors has mostly (well, somewhat) ceased, the complexity of the UVM and the earlier VMs on which it is based can be viewed more clearly and with less controversy. And the results are not good. After years of experience working with many multiple clients, it seems the only way out of our current dilemma is to start looking at other languages and development frameworks. For that to happen, major semiconductor companies may need to start funding this type of development again, since it is abundantly clear the EDA vendors are incapable of this level of innovative thinking. Or more kindly, perhaps they feel there is no money in innovation. Either way, major advances in design and verification productivity need to get here sooner rather than later.