What is the difference between int array1 [6] and int array2 [5:0];

SystemVerilog
1

In systemverilog, There is a way to represent array.

int array1 [6];   //Compact declaration
int array2 [5:0]; // Verbose declaration

I think array1 and array2 are the same in fixed size single dimension array.
Why does it have 2 ways for represent way in systemverilog?

2

In reply to UVM_LOVE:

In compact form, you cannot have an index starting from any value you desire. It begins from 0 by default.
In verbose form, you can rather have an array of 10 elements as array[9:0] or array[1:10] and, array[2:11].

Hope it helps :)

3

In reply to UVM_LOVE:

The compact form was put into SystemVerilog to be compatible with C/C++ and other languages. [6] is equivalent to [0:5]. Verilog always required you to specify a left and right bounds.