What is the difference between cache and fifo?

SystemVerilog
1

Hi,

whether We can use both cache and fifo as buffers(small Delay)?

May I know what is the actual difference between them when you are using as “buffer application”?

2

whether We can use both cache and fifo as buffers(small Delay)?
what is the actual difference between them when you are using as “buffer application”?
I see a (fifo) buffer as the constrained storage of a stream of information, such as data sequential items. A cache is more of an associative array with a limited size. Of course, a cache can be used as a buffer, but it would require some supporting logic (e.g., counters) to maintain the write and read addresses for the data items, thus emulating the stream of information being stored and read. A fifo design would run at a faster clock than a cache for the same technology because of it is of less complexity than a cache design.

Ben Cohen Training for VMM, SVA (831) 345-1759
http://www.systemverilog.us/ ben@systemverilog.us

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