What is the between the use of typedef with enum and simple enum declaration?

SystemVerilog
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What is the between the use of typedef with enum and simple enum declaration ?

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In reply to shankar_srininvasan:
You need a typedef if you want more than one variable to share the same enumerations.

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In reply to shankar_srininvasan:

typedef is used to declare user defined types, so by declaring a typedef enum you are creating a new data type which can be used to create variables now. EX :

enum {RED, GREEN} col, col1; // Without typedef

typedef enum {RED, GREEN} color; //With typedef
color col, col1;

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Thanks so much for your valuable response @dave and @rohitk