What is the appropriate way of building uvm testbench?

UVM
1

I have a project to verify OCP protocol, there are some complex tasks.
I can’t build them all from scratch. Tasks get extremely intertwined. Unless I start by simple tasks and then build my way up.
The difficulty is in the fact I cannot test what, I code unless I have a complete environment!
I started from down to top, starting with sequences.

Thank You.

2

In reply to haithamx15:

You have to differentiate between the testbench and the tests. Tests are executed on the testbench and thy can modify your testbench. The best way is to start with the testbench and further on you continue with sequences and tests.
The best and fastest way is to generate an UVM testbench using a framework generaor. There are several tools on the market bur also some free of charge as the code generator from Doulos.
You can find it here:
https://www.doulos.com/knowhow/sysverilog/uvm/

The benefit is you get a complete running environment after creating a few setup files, lasting maybe half a day. And you do not run into all the traps.