What is reg_model.default_map.set_sequencer() and usage?

UVM
,
1

I came across the following in RAL snippet in UVM example when I googling.

 
   ...
   class intermediate_sequencer extends uvm_sequencer #(intermediate_pkt);

   `uvm_component_utils (intermediate_sequencer)

   function new (string name, uvm_component parent);
      super.new(name, parent);
   endfunction : new

   endclass : intermediate_sequencer
    ...
    // set predictor properties
     i2c_predictor = i2c_reg_predictor::type_id::create("i2c_predictor",this);

    // create adapter
    i2c_adapter = reg_to_i2c_adapter::type_id::create("i2c_adapter",this);

    // set predictor properties
    i2c_predictor.adapter = i2c_adapter;
    i2c_predictor.map = reg_model.default_map;

    i2c_int_sequencer = intermediate_sequencer::type_id::create("i2c_int_sequencer", this);
    i2c_int_sequence = i2c_intermediate_sequence::type_id::create("i2c_int_sequence");

    ...
    reg_model.default_map.set_sequencer(i2c_int_sequencer, i2c_adapter);

Especially, I want to know the usage of the below

reg_model.default_map.set_sequencer(i2c_int_sequencer, i2c_adapter);

I can’t find any relationship between .default_map and .set_sequencer. Also I didn’t get “set_sequencer(i2c_int_sequencer, i2c_adapter)” meaning. why do I need this?

https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/uvm_reg_block-svh.html#uvm_reg_block.set_default_map
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1b/html/files/seq/uvm_sequence_item-svh.html#uvm_sequence_item.set_sequencer

I only find a similar snippet code “regmodel.default_map.set_sequencer(reg_seqr,null);”
in https://www.accellera.org/images/downloads/standards/uvm/uvm_users_guide_1.2.pdf in 129 Page.
Why is “null” used here?