What is difference between rsp_1[*2] & $stable(rsp_1) in System Verilog assertion?

In reply to SUNODH:

They are very different.

*rsp_1[2] is a sequence saying that rsp_1 must be true in the current cycle and true in the next cycle.

$stable(rsp_1) is a boolean function returning true if rsp_1 has the same value it had in the previous cycle.

You cannot use the select/condition operator on a sequence. You can use an implication.

property p_rsp_req
@(posedge clk)  if (req) rsp_1[*2] else rsp_2[*2];
endproperty : p_rsp_req 

Your requirements say nothing about when the 2 clock cycles rsp_1 must be asserted in relation to when req is asserted, or what rsp_1 should be if req is not true