what is Asic respins in verification?
can any one tell me
please
In reply to lalithjithan:
what is Asic respins in verification?
There are several cases when after an ASIC is finalized into a chip it fails with real hardware. The bug has to be analyzed, fixed, and the ASIC has to go through a respin, meaning getting built again.
I vividly remember the case of a chip that interfaces with a uP that had a backside high-speed memory interface and a front-side serial IO bus. The uP controlled the internal transfer between the backside and front-side through a set of sync signals. That handshake was complex and there was an error in communication between the uP vendor and us (I think it was a weird interface and conditions designed for optimization in the uP performance that was really understood by very few uP engineers but was not well documented). As a result, the completed ASIC eventually got latched into a hold state on the front-side. After further analysis with the uP vendor, a better understanding of that interface was understood and the chip had to be respun to address the front-side operation.
Respins are expensive in terms of cost and deliveries, and that is why good specs, randomized simulations, and thorough verifications are very very important.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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