What is actually a grant and handshake procedure in system verilog assertions?Can you please provide significance of both with proper examples

SystemVerilog
1

What is actually a grant and handshake procedure in system verilog assertions?Can you please provide significance of both with proper examples

2

In reply to swapnilsrf9:

  1. A handshake is a synchronization scheme between two entities that need to commnunicate
  2. An assertion is an expression of the requirements, and a verification that those requirements are met. Thus, the handshake protocol and the assertion are two different concepts: one is a protocol, the other a definition of the requirements for that protocol.
  3. An assertion can be expressed in a variety of ways. SVA is a specialized notation to make the expression of those requirements easier, clearer, analyzable, and executable.
  4. Books tend to use the req/ack examples because it is a very familiar model.

A typical example of such an assertion:


ap_reqack: assert property(@(posedge clk) $rose(req) |-> ##[1:5] ack);  
// Any new req should be acknowledged within 1 to 5 cycles

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115