What is a "nested scope"?

SystemVerilog
1

I am puzzled by the following paragraph, can anybody tell me what is a “nested scope”?
“When an identifier is referenced within a scope
— First, the nested scope is searched (see 23.9) (including nested module declarations), including any
identifiers made available through package import declarations.”( IEEE Standard for SystemVerilog)

2

In this context, a nested scope is any region of code inside a compilation unit that creates a new scope. A module declaration creates a scope nested inside a compilation unit. A task declaration inside that module declaration is a nested scope within the module.

Sometimes the term lexical scope is used interchangeably with nested scope, but a nested scope excludes the scope that is the compilation unit. If you have the following code in a file:

int A;
task T;
  int B;
endtask
module M;
  int C;
  task T;
    int D;
    $display(A,,,C,,D);
  endtask
endmodule

The variable A is not declared in a nested scope. The first task T and the module M are not declared in a nested scope, but both create nested scopes. The variables B, C and D are all declared in nested scopes. The second task T creates a nested scope inside the scope M.

A reference is any mention of an identifier that is not a declaration. The $display statement references A and D. The compiler will search for A inside task T, then module M, and will find it the compilation unit. It will find C in module M and D in task T. It will do this search without even knowing where module M eventually gets instantiated.

3

In reply to dave_59:

Thank you Dave!

So, In your example, If I replace "module M" with "class M ", the result will be the same.

However, if "A" is not declared in the compilation unit, the compiler will search the instance hierarchy tree of module M(upwarding search)?
if reference "A" in "class M" and "A" is not declared in the compilation unit, the compiler will report compile error directly, it will not search instance hierarchy tree?
4

In reply to Wanglj:

Yes, you can replace module with class and get the same results.

However, searching the instance hierarchy tree does not happen for simple names like “A”. Verilog will only begin a search of the instance hierarchy for dotted names like “A.B” as well as for function/task references. If “A” was not declared, you should get a compiler error before elaboration.