What are the truncation/conversion rules in this expression?

Given the following code:


logic [3:0] bitc [64] = '{default:4'hf};
logic [8:0] count;

assign count = bitc.sum() with ($countones(item));

The value of count should be 64*4=256 (or 9’h100), but I am seeing the count as 9’h1FF.

Can someone explain the semantics of what is going on?

In reply to a_stod:

It looks like several tools have problems with this code. The correct answer is 256.

This Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please contact your tool vendor directly for support.

In reply to dave_59:

Ok thank you. I just wanted to make sure that it wasn’t a SystemVerilog misunderstanding on my part.