The answer to this question depends on the context.
In the context of a SystemVerilog concurrent assertion, it refers to a sequence or property operator that operates over multiple clock cycles. This would exclude all boolean and arithmetic operators.
In formal linear temporal logic (LTL), it represents an operator that specifies a condition with a past and a future condition. So always, nexttime, until are temporal operators, but implication and ##delay are not.
In dynamic simulation, event controls (#delay, ~@(), wait() could be considered temporal operators.
In the context of a SystemVerilog concurrent assertion, it refers to a sequence or property operator that operates over multiple clock cycles. This would exclude all boolean and arithmetic operators.
Would this mean that both implication operators , clock delay ##delay are temporal operators ?