What are benefits of C model based verification of RTL design?

SystemVerilog
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1

Hello,

What are benefits of C model based verification of RTL design? how is a C model instantiated in systemverilog?

2

In reply to unmay7:
Key benefits are:

  • The C models may already exist and using them avoids re-writing them in SystemVerilog
  • Most C models written at higher levels of abstraction will be faster than the same models written in SystemVerilog. The key is getting into higher levels off abstraction without being bogged down with pin-level timing accuracy that would be more efficient written in SystemVerilog.
  • The ability to use your C models in a pure C environment outside of RTL verification

I already gave you some links for integrating C code:

In reply to unmay7:

https://verificationacademy.com/forums/systemverilog/how-c-function-able-call-time-consuming-sv-task#reply-99746