WDT Verification UVM

UVM
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1

Hi everyone,

I am a newbie on UVM verification and trying to verify for a WDT design by UVM evironment.
WDT Description:

  • Inside a WDT, it has a clock mux between two external clocks(clk1 and clk2) to iclk based on the control of clk_sel signal. If clk_sel =1 iclk =clk1, otherwise iclk = clk2.
  • if wr_en=0 It writes the configured data into WDT. wr_en=1 it reads out data from WDT register
  • When wt_en=1, the counter will count up, and when it reaches the timer set, wt_int interrupts for a specified periods. the timer set and interrupt periods of wt are controlled by timer_sel[1:0] and interrupt_len[1:0]
  • If wt_rst =1 → WDt reset

Could anyone help me on the basic steps what I need to do for this verification.
For the clock mux case, how uvm helps me to check the iclk whether it’s right to the spec when I control clk_sel.

Any help I highly appreciate it

Stephan