Want to replace wait statement with while

SystemVerilog
,
1

Hii,

I have one wait statement in monitor :

wait( `rx_mon_rx_if.rx_dv && !`rx_mon_rx_if.rx_er );
$display( $time,,"AFTER_WAIT");

Output for this code is : 8708 AFTER WAIT

How to replace this statement with while ?

I have tried like this :

while( !(`rx_mon_rx_if.rx_dv && !`rx_mon_rx_if.rx_er ) )
begin
    @( posedge vif_tx.gtx_clk );
end
$display( $time,,"AFTER_WAIT");

In this while loop snippet display statement is not even printing.

2

In reply to Jaydip_Solanki:

Typically one would write this using iff instead of a using while loop.

@(posedge vif_tx.gtx_clk iff `rx_mon_rx_if.rx_dv && !`rx_mon_rx_if.rx_er)

Are rx_dv and rx_er being driven with nonblocking assignments on the same clock?