Waiting for change in value of packed array

SystemVerilog
,
1

Hello all,
I have 2 packed array a and b;

bit [5:0] a;
bit [5:0] b = 6’h5;

Actually i want to monitor when the values of both get equal…
I tried

wait(a == b) ;

also

@(a == b);

The value of b is fixed but the value of packed array “a” changes i want to wait till the point i get the value of “a” packed array same as that of “b” packed array. Can i use @ or wait here to take this in account like we do for normal variables in verilog. Somehow can we monitor the change in value of the element of the array like we do for a variable using @(x) …

Thanks…

2

In reply to Verrockon.:

wait(a==b) should have worked. Can you show and explain your issue better?

3

In reply to dave_59:

Yes actually I have a value of one packed array fixed to say 9 , I have another packed array whose value changes continuously as it is an output from a Soc , I need to continuously monitor the value of this packed array …till this output gets equal to the value I want, I should wait.

Also out of curiosity is there some means we can monitor every change in the value of packed array like we have @(var) in verilog.

4

In reply to Verrockon.:

I don’t understand your question. It would help to provide a small executable example of what you want to do.

5

In reply to dave_59:

Sure there is a design soc in which there is an output which is a packed array , I am monitoring the output of that packed array. This is an output from an soc so it is not in my control and it’s value varies. Now i have to monitor this output which is coming out of the soc and wait in my testing environment when the output from the soc gets equals to a value 5. I am trying to code this. How can I implement this. I tried wait( output of soc = value in my testing environment) so that the control won’t go beyond this wait statement till the output from soc gets equal to my testing value. It’s just that I need to monitor the value of packed array coming out of an uncontrolled soc.
I made a testing variable as
bit [5:0] b = 6’h5 ;
Taking output of soc in another variable say a declared as
But [5:0] a;

Now waiting for a to get equal to b as
Wait(a ==b);

But the above wait is going long as a” gets value 5 as I do observe in waveform but the same isn’t getting captured in my testing environment. Thought if there is an alternative to this or can use some other method.

6

In reply to Verrockon.:

I still don’t understand your problem. Maybe it is something else besides the wait statement. It would really help to show a complete example showing the behavior you are seeing and describing what you would like to see instead. Like this:

module SOC(input bit clk, output logic [5:0] output_of_soc);
  initial begin
    repeat(5) @(posedge clk);
    output_of_soc = 5;
  end
endmodule
module testbench;
  bit clock;
  bit [5:0] a,b;

  SOC dut(clock,a);

  always #5 clock=!clock; 
  initial begin
    b = 5;
    wait(a==b) $info("output went to %d",b);
    $finish;
  end
endmodule
7

In reply to dave_59:

Thanks Dave for explaining … this works