Wait statements

SystemVerilog
,
1

I’m confuse regarding the exact meaning of wait statement.

What does happen in this case:

forever begin
    wait (vif.xn_valid == 1'b1);
    @(posedge vif.clk);
end

Is wait statement is blocking statement?
Is the

@(posedge vif.clk)

exexuted each loop (regardless the evaluation of the wait expression) ?

And in this case:

forever begin
    wait(vif.cyc_tic == 1'b1) @(posedge vif.clk) #0 fact_log2_samp_t = vif.fact_log2_samp;
end

Is the code after the wait (

#0 fact_log2_samp_t = vif.fact_log2_samp;

) executed only if the evaluation of the wait expression is true)?

2

In reply to saritr:

Is wait statement is blocking statement?

Yes. From section 9.4.3:

The wait statement shall evaluate a condition; and, if it is not true (as defined in 12.4), the procedural statements following the wait statement shall remain blocked until that condition becomes true before continuing.

Based on that, the answer to your second question is ‘no’, and third question is ‘yes’.