Wait for signal value in a task with timeout

SystemVerilog
,
3

In reply to dave_59:

Why add another bit “timed_out” instead of using join_any?

task automatic timeout(ref logic signal,input logic value,input time timeout_value);
           fork begin
              fork
                begin
                  #timeout_value;
                  `uvm_error(....
                end
                begin
                  wait(signal === value);
                end
             join_any
             disable fork;
           end join
endtask