Vivado UVM Simulation Memory Leak

In reply to cgales:

In reply to atabey:
Your latest post contradicts your earlier post. You earlier stated “the memory usage increases gradually forever when the simulation starts to run”, but your last post states that simulation finishes successfully. Does the simulation run forever or does it finish?
If your simulation finishes successfully, then I don’t understand your comment about memory leaks. It seems like your testbench is functioning correctly.

I keep the number of items being sent limited, so simulation should finish at some point. I can change the desired number, so the simulation runtime changes. For example, if number of items double, simulation time and memory usage double also. This issue does not allow simulation run for longer packets.