In reply to cgales:
In reply to atabey:
You are describing functional issues, not memory leaks.
You need to start with the basics and debug your environment:
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Are your clocks/reset connected and functional?
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Is your DUT/interfaces connected correctly?
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Does your simulation finish?
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Do your drivers work? Do you see transactions correct at the DUT interfaces?
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Monitor work?
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Scoreboards work?
You have some significant issues in your code, as well as some extremely poor implementations of the AXI streaming protocol. To start, your sequence item should encapsulate an entire data stream packet, not each individual beat. The driver should handle the protocol handshake, and not just mirror sequence item data to the interface. -
Clock and reset signals are connected to DUT. I do not know what is functional in clock/reset.
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Yes. Interfaces are connected correctly. I can see the transactions in the waveform analyzer.
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Simulation finishes succesfuly.
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I think drivers corrrectly runs, so I can see the expected changes in the waveform analyzer.
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Monitor and scoreboard are fine in simulation. Monitor can send the packets to scoreboard.
Thanks for your comments about the code. I do not understand how to encapsulae entire data with one sequence item. I will think about the method. The driver handles the protocol handshake. I developed the code to wait the ready signal if there is a valid data in the interface. The lines for handshake in axis_driver code:
do begin
@(posedge vif.clk);
end while (req.valid && !vif.ready);
do begin
@(posedge vif.clk);
end while (req.ready && !vif.valid);