Virtual class invokes base-class function instead of overwritten one

SystemVerilog
,
1

Consider the following two classes:


virtual class A;
  virtual function void do_sth_abstract();
    $display("A");
  endfunction;

  task do_sth();
      do_sth_abstract();
  endtask
endclass

class B extends A;
  function void do_sth_abstract();
    $display("B");
  endfunction
endclass

module top;
  initial begin
    B b = new B();
    b.do_sth();
  end
endmodule

If I execute B::do_sth, why does it print “A”? I want to use the class A as an abstract class, which uses the overwritten functions from B.

How can I get this behavior in SystemVerilog?

Thanks in advance!
Tom

2

In reply to razer6:

There is mo B::run in your example. please edit it to show a complete executable example, including construction of the objects.

3

In reply to dave_59:

Could you also drop in the code of where you are invoking the method call and object declarations?

[EDIT] Dave beat me to it! ;)

4

In reply to bmorris:

Sorry, B::run was intended to be B::do_sth(). I’ve updated the samples.

5

In reply to razer6:

It is printing B when I run it:

Only change I made was breaking this into 2 statements (wouldn’t compile):
b = new B();

[EDIT] Also, If you look at 5.6.3 SystemVerilog for Verification (Chris Spear):
“You should avoid declaring a handle and calling the constructor, new, all in one statement. … It can create ordering problems”